The invention relates to a semiconductor device chip, to a semiconductor device system with a plurality of, in one embodiment stacked, semiconductor device chips, and to a method for operating a semiconductor device system.
Semiconductor devices, e.g., integrated (analog or digital) computing circuits, semiconductor memory devices such as, for instance, functional memory devices (PLAs, PALs, etc.) and table memory devices (e.g., ROMs or RAMs, in one embodiment SRAMs and DRAMs), etc. are subject to comprehensive tests during and after their manufacturing processes.
For the common manufacturing of a plurality of (in general identical) semiconductor devices, a wafer (i.e. a thin disc of monocrystalline silicon) is used. The wafer is processed appropriately (e.g., subject successively to a plurality of coating, exposure, etching, diffusion, and implantation processes, etc.), and subsequently e.g., sawn apart (or e.g., scratched, and broken), so that individual device chips are then available.
During the manufacturing of semiconductor devices (e.g., of DRAMS (Dynamic Random Access Memories or dynamic read-write memories)), in one embodiment DDR-DRAMs (Double Data Rate—DRAMs) the (semi-finished or finished) devices that are still available on the wafer may be subject to appropriate tests (e.g., “wafer tests”).
One or a plurality of further tests may be performed, for instance, after the incorporation of the semiconductor devices or device chips in semiconductor device packages, and/or e.g., after the incorporation of the semiconductor device packages (along with the respectively included semiconductor devices or device chips) in electronic modules, e.g., memory modules (so-called “module tests”).
As device packages, appropriate plug or surface-mountable packages, e.g., BGA (Ball Grid Array) packages, etc. may, for instance, be used.
During the incorporation of a device or device chip in a package, connections—pads provided at the semiconductor device are connected with connections—pins provided at the device package by using appropriate bonding wires.
In one single device package, instead of one single semiconductor device or device chip, in one embodiment DRAM chip, a plurality of, e.g., two (or e.g., four) devices, etc. may in one embodiment also be arranged. By the use of such a package with a plurality of chips (“multiple chip package”) it is possible to increase the package density.
Part of the connections of a first device arranged in a respective multiple chip package and part of the connections of a second device arranged in a respective multiple chip package, etc. may be connected by using bonding wires with one and the same device package pins, and another part of the connections, in one embodiment, for instance, CS connections (chip select connections), etc., with pins, e.g., chip select pins, etc. that are separate for every device.
If, in the above-mentioned semiconductor device tests, it is determined that a chip that is incorporated in a multiple chip package is defective, but the multiple chip package includes at least one further faultless chip, one is anxious to nevertheless use the multiple chip package (e.g., a “dual die device” including two chips then as a “single die device” instead as a “dual die device” (or e.g., a “four fold stack device” including four chips then as a “dual die device” instead as a “four fold stack device” etc.)).
After the incorporation of the multiple chip package in an electronic module, e.g., memory module, the respective defective chip is controlled such by the applying of signals to pins of the multiple chip package that it consumes only relatively little power.
The remaining power consumption of the defective chip may nevertheless still be relatively high.
For these and other reasons, there is a need for the present invention.